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Electronics: I have extensive experience in the design of both analogue (general glue circuitry, OP amps, filters, video and RF) and digital systems (FPGAs, VLSI design, microprocessor, multiprocessor design, array processor design) for both commercial and University research based projects.
Programming Languages: I am experienced in the following languages (using UNIX, DOS and Windows NT),
Web/Internet: I have an in depth knlowledge of a broad range of Internet technologies.
Wireless Data: The design of WAP based applications and related software, including database integration using Java Servlets on the Nokia WAP server (integration to other data sources is also possible, including most legacy systems). I am a founder of, and was previously employed by Yospace Ltd, a company specialising in the development of wireless Internet systems.
University Teaching: I have been employed by Royal Holloway, University of London, since September 1990 as a lecturer in Computer Science and Electronics. I have designed and taught courses in Digital Electronics, Computer Architecture, Assembly language programming. I have also taught pre-prepared courses in Java programming, and Internet/Intranet systems.
Industrial Training: I work as a freelance instructor for the Learning Tree International. I teach the following courses:
I have also developed course material for the Learning Tree International. I am the author of course 489 (Building Web Sites with JavaScript). I am the co-author of course 485 (Netscape SuiteSpot Servers for Internet/Intranet Development). I have also produced and presented numerous customised On-Site versions of the above courses for specific Learning Tree International clients.
My university based research work falls into two main areas; image processing and neural networks. Although I am involved in the algorithmic side of both fields, especially with low level image processing, most of my efforts have been directed to the design of appropriate high speed hardware and software implementations.
For image processing applications this has resulted in the design of several high speed sequential processors, bit serial SIMD array processors, and various full custom CMOS VLSI devices, designed to implement a variety of real time image processing applications. I have a good working knowledge of low level image processing algorithms; noise removal, edge and corner detection, circular object detection, line detection, and enhancement through Fourier processing. My algorithmic research involves the design of fast rank filtering algorithms for noise removal, and especially for corner detection.
My most recent work has been concerned with the development of novel massively parallel stochastic bit stream hardware for neural implementations. The aim of this research has been to develop extremely compact hardware that exploits the statistical nature of real valued signals encoded as probabilistic bit streams, thus allowing large numbers of neurons to be fabricated within a single VLSI device, or gate array. The resulting bit stream architectures have been carefully designed to allow the implementation of both feed forward and recurrent networks. In addition to this, the design of the individual bit stream neurons allows for the possiblity of `on-chip' gradient descent learning to be built in to a given network architecture. This is made possible by the ability of the individual neurons to generate their output derivatives with very little cost in additional circuitry.
I am also heavily involved in the development of extremely high speed opto-electronic neural networks. These architectures are also based on the techniques of stochastic computing, but here the individual neurons are formed from the novel application of integrated micron waveguide devices and optical percolation devices (the subject of a recent patent, by myself and colleagues).
Recently I have become involved in the design of high speed optical CDMA components. These devices are based on the integrated waveguide technology developed by the DRA at Malvern (UK). I have also become involved in the hardware design of a novel wireless networking device.